Overview In this role, you help ensure the silicon you design and verify meets tight quality and yield targets for Apple's high-performance SoCs. You'll work within the Silicon Technologies group to drive physical verification and signoff readiness for tapeout, collaborating with CAD, package, and floorplanning teams. You'll tackle complex verification challenges across LVS/DRC, manufacturing, and lithography, delivering robust, power-efficient processors. Your work directly influences product reliability and performance at scale. Compensation / Benefitsmedical and dental coverageretirement benefitsemployee stock programsrelocationtuition reimbursementbonus potential ResponsibilitiesPerform physical verification checks (LVS, DRC, DFM/DFY, lithography) at chip and block levelsCollaborate with CAD/Technology and implementation teams to drive signoff closure for tapeoutLead schedules and support cross-functional engineering effortsContribute to padring, bump, RDL design and coordinate with package and floorplan teams Key requirementsBS and 3+ years of relevant industry experienceExperience with physical verification flows such as DRC/LVS/ANT/HVDRC signoff and full-chip integration methodologyESD and macro placement design guidelines; back-end verification for digital and analog mixed-signalScripting skills: perl/python/tcl for debugging and automationExperience with industry-standard physical verification tools (Mentor Calibre, Synopsys ICV)Tapeout experience with successful signoffLayout design experience is a pluscross-functional collaborationproblem solvingstrong communicationphysical verification flows (DRC/LVS/ANT/HVDRC)full-chip integration methodologyESD and macro placement guidelines
Not specified in the original listing.
Not specified in the original listing.