Overview In this role you will drive high-performance, low-power processor integration and verification at chip level, collaborating with multiple disciplines to enable fast tapeouts. You'll own key CAD and physical design steps, from floorplanning to final layout verification, delivering robust chip integration across the SOC. You will work to ensure power, timing, and signal integrity meet Apple's performance and quality standards for products reaching millions of customers. This is a hands-on, cross-functional role at the heart of Apple's hardware innovation, offering meaningful impact on next generation processors. ResponsibilitiesFull chip floorplanning and area optimizationOwn chip-level place and route and PDV verificationDevelop and validate Power Grid and routability analysesLead EM/IR, electrical verification, and formal verification at block and chip levelCollaborate with implementation/CAD teams to drive tapeout signoffCoordinate with the SOC team to meet IP delivery requirementsContribute to CAD and physical design methodologies and flow developmentAutomate tasks through scripting to improve debugging efficiency Key requirementsBS degree and 3+ years of relevant industry experienceScripting experience in Perl or TCLteam collaborationproblem solvingself-motivationPhysical Design knowledge: Floorplanning, Partitioning, Budgeting, Place and Route, Physical VerificationPower Grid and Clock specification developmentLow Power Design, EM/IR, SIGEM Analysis, Formal Verification, PDV
Not specified in the original listing.
Not specified in the original listing.
Golden Apple Transportation is a small, privately owned transportation company with over 10 years of experience serving schools and other clients. They focus on maintaining high safety standards and dependable service while fostering a strong sense o... Read More