Overview In this role you will own the end-to-end testing architecture, strategy, and execution for next-generation products and infrastructure. You will lead a cross-functional team of test hardware and software engineers, shaping DFT/diagnostic solutions and test plans to maximize coverage and throughput. You'll collaborate with top silicon partners to embed BIST and boundary scan, driving yield improvements and scalable test frameworks. This position offers impact across design, manufacturing, and roadmap alignment in a fast-paced hardware environment. ResponsibilitiesLead and develop a multi-disciplinary test hardware and software teamOwn DFT/DFx strategy and early design reviews to maximize test accessCollaborate with tier-1 silicon partners to embed BIST and boundary-scan architecturesDefine unified product test specifications and coverage matricesOversee ICT, FCT, SLT, and ESS/Burn-in solutions and their deploymentAnalyze production data to reduce false failures, improve test stability, and optimize yieldProvide hands-on guidance for NPI test vehicle bring-up and fixture qualification Key requirements5+ years leading multi-disciplinary test teamsExperience deploying complex test vectors for high-speed digital systems or working with tier-1 silicon providersExpert knowledge of DFT, IEEE 1149.x (JTAG), high-speed serial links (PCIe Gen 5/6, SerDes)Instrumentation automation and programming frameworks (Python, C/C++, LabVIEW)Data mining/SPC for manufacturing process controlStrong project management and metrics-driven problem solving; Six Sigma Black Belt preferredleadershipmentorshipcross-functional collaborationDFT methodologiesIEEE 1149.x Boundary Scan (JTAG)High-speed serial interfaces (PCIe Gen 5/6, SerDes)
Not specified in the original listing.
Not specified in the original listing.
