Overview As a Sr. SoC Power Engineer on the MLA team, you model and estimate power across RTL to netlist and drive reductions in power for AI accelerators. You will collaborate with architects, designers, verification, and physical design to define best practices and achieve accurate power predictions. You enable lab measurements, IR and thermal analyses, and power rollups to inform design decisions. This role offers impact on cutting-edge Inferentia and Trainium chips through cross-functional work and data-driven power optimization. Compensation / Benefitshealth insurance (medical, dental, vision)401(k) matchingpaid time offparenteral leaveRSU eligibilitysign-on payments ResponsibilitiesPerform full-chip power analysis and modelling from RTL to gate-level netlistDevelop and maintain dashboards for power rollupsCollaborate with designers, architects, verification, and physical design to create IR, thermal, and power estimation vectorsProvide design feedback to reduce power consumptionConduct lab power measurements and correlate with simulationsCollaborate with emulation engineers to model chip-level power usage Key requirementsBachelor's degree in EE/CS or related fields (BS with 6+ years or MS with 5+ years or PhD with 3+ years)Expertise in power analysis tools (PrimePower, PowerArtist, or similar)Deep circuit-level power understandingAbility to give actionable power-reduction feedback to RTL and Physical DesignersScripting proficiency (Tcl, Perl, Python or similar)Strong understanding of Physical Design, EM/IR, Power Integrity, and Thermal at die, package, board, server levelsExperience with lab power analysis and hardware measurementsstrong collaboration with cross-functional teamsdetail-oriented analytical mindsetclear technical communicationPower analysis tools: PrimePower, PowerArtistCircuit-level power modelingLDI/IR/EM management knowledge
Not specified in the original listing.
Not specified in the original listing.