Overview

Job DescriptionJob DescriptionPlease Note:To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology TogetherOur technology solutions power the tools you use every day including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.Job Title Senior Physical Design AI/ML Engineer, Logic Pathfinding LabWhat You'll DoWe are looking for physical design engineers who have demonstrated skills in applying AI / Machine Learning tools in improving design simulation accuracy and throughput in predicting design performance, power, and area (PPA). Experience in optimization of design-technology co-optimization (DTCO) knobs in advanced logic nodes (2nm or beyond) is preferred.The candidate will be a key technical member of the Logic Pathfinding Lab, part of the Samsung Semiconductor Inc (SSI) in San Jose. He or she will join a team of experts in researching and evaluating advanced technology options, and assisting in knowledge / technology transfer to the Samsung Logic Technology Development (TD) in Korea. The successful candidate will be responsible for researching and evaluating new device architectures, materials, and integration schemes through chip design metrics to meet the need of sub-2nm technology nodes. The candidate should have demonstrated skills and experience in standard cell architecture creation, logic cell library characterizations Place and Route, Process Design Kit (PDK) generation, and a strong understanding of Logic process integration. The candidate should have excellent communication skills, and be able to collaborate with and guide multiple organizations, including research consortia.Location: Daily onsite presence at our San Jose office/headquarters in alignment with our Flexible Work policyReports to: Sr DirectorDirect Reports: N/ADesign, build, and implement machine learning and generative models to optimize chip layout designs to maximize performance, power, and area (PPA) efficiency, while using explicit domain knowledge of hardware design rules and constraintsAutomate and accelerate Design Implementation steps such as Floor-planning, Placement and Routing, Clock Tree Synthesis, using exploratory PDKs developed by the teamAutomate and accelerate Verification steps such as Design Rule Checks (DRC) and Layout versus Schematic (LVS) Checks using exploratory PDKs developed by the teamCollaborate with other team members to automate all aspects of exploratory PDK generation, including developing automated QA systemsApplying machine learning techniques to extract and develop correlations among data in different domains, e.g. device, RO benchmark circuits, larger circuit blocks, at different operating conditionsDevelop internal benchmarking capability based on available data, modeling, or learning from multiple sources, and create assessments to share with internal R&D teamComplete other responsibilities as assigned.What You BringPhD with industry experience preferredRTL synthesis, place and route, and timing analysis skillsUnderstanding of clock and power delivery network schemesHands-on experience on machine learning or deep learning projects for scientific and/or engineering applications, e.g., regression, surrogate modeling, inverse design, graph neural networksStrong Python and/or C++ skills, including expertise in machine learning packages like PyTorch and TensorflowExperience in using Bayesian optimization and/or active learning fram