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Senior Architect, IP Methodology Engineering

Date Posted: May 28, 2026
Yearly: £ - £
Job is expired

Job Detail

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    Location Sunnyvale, Baja California, United States of America
  • desktop_windows
    Job Type: Any
  • schedule
    Shift:
  • analytics
    Career Level:
  • group
    Positions:
  • calendar_view_day
    Experience:
  • male
    Gender: No Preference
  • school
    Degree:
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    Apply Before: Jun 28, 2026

Job Description

Overview

At Synopsys, the Senior Architect in IP Methodology Engineering will lead the development of standardized front-end design methodologies and platforms within the semiconductor industry. This role involves driving innovation and delivering high-quality solutions that enhance productivity, performance, power efficiency, and product quality.

Key responsibilities

  • Develop standardized front-end design methodologies and platforms.
  • Promote best practices leveraging advanced tools and flows.
  • Provide technical vision and strategy for next generation EDA tool flows.
  • Collaborate with cross-functional engineering teams.
  • Represent Synopsys at industry conferences and customer engagements.
  • Mentor and coach engineering talent.

Required skills

  • 15+ years of experience in semiconductor IP development and EDA tools
  • Expertise in front-end RTL design and low-power techniques
  • Architecting and deploying EDA platforms for cross-functional organizations
  • Strong understanding of IP protocol standards including PCIe, DDR, and Ethernet
  • Proficiency with Verilog and System Verilog
  • Experience with timing analysis and power optimization

What the company offers

  • Comprehensive health, wellness, and financial benefits
  • Annual bonus and equity opportunities
  • Inclusive culture that values diversity

Skills Required

Company Overview

Sunnyvale, Baja California, United States of America

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, empowering the creation of high-performance silicon chips and software content. Read More

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