Overview As a Resolution Enhancement Techniques (RET) Engineer, you develop RET and OPC solutions to improve wafer pattern fidelity for next-gen memory technologies. You will collaborate across technology development and manufacturing to enhance reticle solutions and tapeout methodologies. You'll lead complex mask and lithography optimization projects and mentor other engineers, applying AI-enabled approaches to engineering. This role offers a direct impact on product quality and technology advancement within a world-class team. Compensation / Benefitsmedical, dental, and vision plansrobust paid time-offpaid holidaysincome protection programspaid family leavebenefits guide available online ResponsibilitiesDevelop and implement RET and OPC solutions to improve pattern fidelity, manufacturability, and yieldOptimize lithography methodologies, software capabilities, and tapeout processes for performance and efficiencyAnalyze patterning issues, identify root causes, and drive corrective actions across R&D and manufacturingLead complex mask development and lithography optimization projects across engineering teamsMentor engineers and promote best practices and knowledge sharing, including AI-enabled engineering approaches Key requirementsBachelor's degree in Electrical Engineering, Materials Science, Physics, Chemical Engineering, or related field6+ years experience in RET, OPC, lithography, or mask developmentExperience developing and applying RET and OPC methodologies for semiconductor patterningStrong understanding of EUV lithography, optics, diffraction, resist behavior, and advanced patterning techniquesExperience with lithography simulation tools such as Sentaurus Litho, ProLith, or similarCross-functional collaborationMentoring and leadershipProblem solving and analytical thinkingEUV lithographyOptics and diffractionRET and OPC methodologies
Not specified in the original listing.
Not specified in the original listing.
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