Overview In this role you drive the design and optimization of high-speed IO and clocking circuits for DRAM products. You will model, verify, and validate signaling and timing to meet full-chip specifications, collaborating with SI, process, and product teams. You'll push speed and bandwidth through circuit-level innovations and contribute to next-generation process nodes. This is a hands-on role in a world-leading semiconductor company with a strong focus on impact and cross-functional teamwork. Compensation / Benefitsmedical, dental and vision planspaid time-offpaid holidayspaid family leavebenefits guide available on wellbeing and professional growth focus ResponsibilitiesDesign, optimize, and verify high-speed IO and clocking circuits for new DRAM productsApply advanced high-speed circuit techniques and assess IO/data-path performance against specificationsDevelop modeling and simulation methodologies to capture key metrics and system-level impactCompare silicon performance with simulations and support correlation activities with SICollaborate with process integration and transistor modeling teams for future process nodes Key requirementsMSEE + 10 years or BSEE + 12 years in analog/mixed-signal circuit designProficiency with UNIX and Cadence design environmentUnderstanding of device physics and CMOS processing basicsAbility to supervise layout and implement good high-speed layout practicesStrong communication skills and ability to convey technical conceptsMental agility to work across product types and parallel teamsstrong communicationmentoring and coachingcross-functional collaborationhigh-speed transmitter/receiver and clocking circuit designchannel modeling and characterizationtransceiver noise and timing budget analysis
Not specified in the original listing.
Not specified in the original listing.
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