Overview In this role you contribute to advanced digital IC and SoC implementation at Battelle, focusing on physical design, timing closure, power optimization, verification, and tape-out across leading semiconductor technologies. You will collaborate with RTL, verification, foundry, and tech teams to deliver secure, high-performance microelectronics for government and commercial clients. The position offers exposure to cutting-edge programs and a chance to shape signoff through robust design methods. This role combines hands-on design with process development to enable reliable, scalable hardware solutions. Compensation / Benefitsflexible, compressed work schedule with every other Friday offhybrid work model: 60% in-office, 40% remotepaid time off for work-life balancemedical, dental, and vision coverage with wellness incentives401(k) retirement plan with company matchtuition assistance ResponsibilitiesExecute physical design from netlist to GDSIIPerform floor planning, power planning, and pin placementConduct placement optimization and clock tree synthesisPerform detailed routing and optimization for timing, power, and areaAchieve timing closure across corners and modesConduct power analysis and implement power reduction techniquesPerform signal integrity analysis and resolve SI/IR drop violationsExecute physical verification checks (DRC, LVS, antenna, ERC)Generate timing constraints and perform static timing analysisCollaborate with front-end design and verification teamsWork with foundry and technology teams on design rule complianceCreate and maintain physical design documentation and reportsDevelop and improve physical design methodologies and flowsSupport signoff activities and tape-out preparationsDebug and resolve design issues found during physical verification Key requirementsBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field3+ years of physical design experienceStrong experience in physical design flow (floor planning, placement, clock tree synthesis, routing, optimization)Expertise in static timing analysis (STA) and timing closure techniquesKnowledge of power analysis and power optimization methodologiesExperience with signal integrity, IR drop analysis, and EM/electromigration analysisProficiency with physical verification (DRC, LVS, antenna, ERC)Hands-on experience with industry-standard backend EDA tools (Cadence Innovus)Scripting skills (TCL, Python) for automation and flow developmentUnderstanding of process technology nodes and design rulesKnowledge of clock domain crossing (CDC) and timing constraintsFamiliarity with standard cell libraries and design kitsKnowledge of Version Control (Git)Must be a US citizen and able to obtain and maintain US Government security clearancecollaborationcommunicationproblem-solvingCadence Innovusstatic timing analysis (STA)timing closure techniques
Not specified in the original listing.
Not specified in the original listing.
